The present invention relates to a phase synchronization method to synchronize phases, a phase synchronization circuit, and a read channel circuit in an extended partial response regeneration system using (1, 7) RLL codes.
For a storage device, such as a magnetic recording device and an optical recording device, high density recording is demanded. Therefore, in a magnetic recording device, a partial response recording system is used. For partial response recording, 8/9 codes are used. 8/9 codes are codes that convert 8 bits to 9 bits. 8/9 codes are codes where the number of xe2x80x9c0sxe2x80x9d between xe2x80x9c1xe2x80x9d and xe2x80x9c1xe2x80x9d is a minimum of 0 and a maximum of 4.
In this magnetic recording device, high-density recording can be implemented by decreasing the size of magnetic particles of the magnetic recording medium. However, if the size of magnetic particles is decreased, thermal relaxation, where the direction of magnetic domain changes due to heat, tends to occur. This thermal relaxation deletes magnetic information. Therefore (1, 7) RLL codes with low recording frequency are used instead of using 8/9 codes.
(1, 7) RLL codes are codes where the number of xe2x80x9c0sxe2x80x9d between xe2x80x9c1xe2x80x9d and xe2x80x9c1xe2x80x9d is a minimum of 1 and a maximum of 7. Since one xe2x80x9c0xe2x80x9d is always inserted between xe2x80x9c1xe2x80x9d and xe2x80x9c1xe2x80x9d, recording frequency is decreased. By using this codes, the loss of magnetic information by thermal relaxation can be prevented.
For the (1, 7) RLL codes, an extended partial response recording system, such as EPR (Extended Partial Response) and EEPR (Extended Extended Partial Response) having a low frequency spectrum, is used. In such a system, a phase synchronization method for synchronizing clocks stably is demanded.
FIG. 17 is a block diagram depicting a prior art, FIG. 18 is a spectrum diagram of a partial response, and FIG. 19(A), FIG. 19(B) and FIG. 19(C) are diagrams depicting partial responses.
FIG. 17 shows a recording channel and a read channel of a partial response magnetic recording. As FIG. 17 shows, the recording channel has a coder 93 that converts recording data to (1, 7) codes. The output of the coder 93 is pre-coded by the pre-coder 94, then is written to the magnetic disk 91 by the magnetic head 90 via the amplifier 95.
The recorded data is read from the magnetic disk 91 by the magnetic head 90. The output of the magnetic head 90 is input to the PR equalizer 98 via the amplifier 97. The PR equalizer 98 executes partial response equalization. The output is sampled by the sampler 99. An analog/digital converter is normally used for the sampler 99.
The output of the sampler 99 is input to a five-value judgment unit 100 for five-value judgment. The five-value judgment output is input to the maximum-likelihood detector 101 where the maximum-likelihood value is detected. And the detection signal is input to the (1xe2x88x92D) equalizer 102 that has a (1xe2x88x92D) equalization characteristic. The (1xe2x88x92D) equalizer 102 cancels the characteristic of the pre-coder 94. Furthermore, the output of the (1xe2x88x92D) equalizer 102 is decoded by the (1, 7) decoder 103. By doing this, regeneration data is obtained.
The judgment output of the five-value decision unit 100 and the sample output are input to the phase error computing unit 104. The phase error computing unit 104 computes the phase error from the judgment output and the sample output. This error is smoothed by the loop filter 105. And the voltage control oscillator (VCO) 106 generates a clock at a frequency (phase) according to the output of the loop filter 105. This clock is used as a sampling clock of the sampler 99.
Since these (1, 7) RLL codes are codes having at least one xe2x80x9c0xe2x80x9d between xe2x80x9c1xe2x80x9d and xe2x80x9c1xe2x80x9d, recording frequency is low. So even if high-density recording is executed, loss of data by thermal relaxation can be prevented.
As FIG. 18 shows, in a partial response, the spectrum of EPR-4 (Extended Partial Response Class-4) has a lower frequency than the spectrum of PR-4 (Partial Response Class-4). In other words, EPR-4 has a higher gain at low frequency. And EEPR-4 (Extended Extended Partial Response Class-4) has an even lower frequency spectrum.
Since (1, 7) RLL codes have a low frequency spectrum, EPR-4 and EEPR-4, where low frequency gain is high, are appropriate. When D is the delay operator, and PR-4 is given by the transfer function (1xe2x88x92D)xc2x7(1+D), then EPR-4 is given by the transfer function (1xe2x88x92D)xc2x7(1+D)xc2x7(1+D). And EEPR-4 is given by (1xe2x88x92D)xc2x7(1+D)xc2x7(1+D)xc2x7(1+D).
As a modification of EPR-4, MEPR-4 (Modified Extended Partial Response Class-4) given by the transfer function (1xe2x88x92D)xc2x7(1+D+D2) and MMEPR-4 (Modified Modified Extended Partial Response Class-4) given by the transfer function (1xe2x88x92D)xc2x7(1+1.5D+D2) are known. As a modification of EEPR-4, MEEPR-4 (Modified Extended Extended Partial Response Class-4) given by the transfer function (1xe2x88x92D)xc2x7(1+D)xc2x7(1+D+D2) and MMEEPR-4 (Modified Modified Extended Extended Partial Response Class-4) given by the transfer function (1xe2x88x92D)xc2x7(1+D)xc2x7(1+1.5D+D2) are known.
This partial response in a broad sense, which includes the transfer formula (1xe2x88x92D)xc2x7(1+(1+a)D+D2), is called an xe2x80x9cextended partial responsexe2x80x9d. Here axe2x89xa70. As FIG. 19(A) shows, the regenerated solitary wave in PR-4 indicates three states, 1, 0 and xe2x88x921. The regenerated solitary wave of EPR-4 (MEPR-4), on the other hand, indicates five states, 2 (1.5), 1, 0, xe2x88x921 and xe2x88x922 (xe2x88x921.5), as shown in FIG. 19(B). Also as FIG. 19(C) shows, the regenerated solitary wave of EEPR-4 (MMEEPR-4) indicates five states, 2 (1.5), 1, 0, xe2x88x921 and xe2x88x922 (xe2x88x921.5).
In this way, the extended partial response in a broad sense has five states. In the extended partial response, the phase synchronization operation has been executed as follows.
As FIG. 20 shows, the magnetic disk 90 has an acquisition area 111 and a data area 112 in each sector 110. In the acquisition area 111, data to train each part of the regeneration circuit is written. In this acquisition area 111, the clock acquisition pattern (phase synchronization pattern) is recorded.
As FIG. 17 shows, an acquisition pattern is read at acquisition. And the state is judged by comparing the amplitude of the acquisition pattern and the slice level. A phase error is computed from the judgment value and the sampling output. The phase of the clock of the voltage control oscillator 106 is synchronized by this computed phase error. At tracking to read the data area, the state of a signal is judged by comparing the amplitude of the read data of the data area 112 with the slice level. From the judgment value and the sample output, a phase error is computed, and the phase of the clock of the voltage control oscillator 106 is synchronized.
For this conventional acquisition pattern, the pattern of a 4T period (T is the sampling interval) has been used for PR-4, as shown in FIG. 21. This pattern is a continuous pattern of xe2x80x9c1sxe2x80x9d in 8/9 codes.
Also conventionally, it is necessary to judge the read signal to be one of five values to compute the phase error, since an extended partial response takes five value states.
At first, in the case of (1, 7) RLL codes, where 2 bits are converted to 3 bits, encoding efficiency is poor compared with 8/9 codes, where 8 bits are converted to 9 bits. Therefore compared with 8/9 codes, track recording density must be increased to record in the case of (1, 7) RLL codes. If a conventional acquisition pattern with a 4T period is used when the track recording density is high like this, the amplitude of the regeneration signal for clock acquisition drops due to inter-symbol interference. As a result, S/N drops and clock acquisition becomes difficult.
Secondly, if (1, 7) RLL codes and the extended partial response in a broad sense are combined, there are five signal states, as described in FIG. 19(B) and FIG. 19(C). Therefore, conventionally five values are judged, and slice levels SL1 and SL2 for five-value judgment are used. If there are many states to judge like this at acquisition before amplitude stabilizes, errors in the judgment result tend to increase. Therefore errors are reflected in the phase errors. As a result, phase acquisition cannot be stably executed at acquisition time.
Thirdly, there are many states to judge at tracking as well, so errors in the judgment result tend to increase and errors are reflected in the phase error. Therefore phase synchronization cannot be stably executed at tracking.
It is an object of the present invention to provide a phase synchronization method for an extended partial response, and for a phase synchronization circuit and a read channel circuit thereof for executing a clock acquisition operation at acquisition at high-speed in an extended partial response suitable for (1, 7) RLL codes.
It is another object of the present invention to provide a phase synchronization method for an extended partial response, and a phase synchronization circuit and a read channel circuit thereof for executing phase synchronization at tracking stably in an extended partial response suitable for (1, 7) RLL codes.
It is still another object of the present invention to provide a phase synchronization method for an extended partial response, and a phase synchronization circuit and a read channel circuit thereof for computing a phase error with less number of state judgments in an extended partial response suitable for (1, 7) RLL codes.
To achieve these objects, the present invention is a phase synchronization method where extended partial response equalization is executed on a recording signal read from the recording medium, then a phase synchronization operation is executed.
The phase synchronization method comprises a step of executing extended partial response equalization having a [1+(1+a)D+D2] (axe2x89xa70) characteristic on the recording signal, a step of sampling the equalization output by clocks, a step of temporarily judging the sample output of the xe2x80x9c100xe2x80x9d gap pattern written in the acquisition area of the recording medium to be [one of] two values (1, xe2x88x921), a step of computing the phase error by the temporal judgment value and the above sample output, a step of adding the above phase error for three samples, and a step of generating clocks with a phase according to the addition result.
At first, the present invention uses the xe2x80x9c100xe2x80x9d of 6T period, which is one of the (1, 7) RLL codes, as a pattern for clock acquisition. Since the pattern of the repeat of xe2x80x9c100xe2x80x9d is a 6T pattern, the period is longer than a conventional 4T pattern. Therefore, even if the track recording density becomes higher, the drop in amplitude due to inter-symbol interference is minimal. Since the amplitude of the regeneration signal of the acquisition pattern is sufficient, clock acquisition can be executed stably.
Secondly, the present invention temporarily judges the sample output to be one of (1, xe2x88x921). In the extended partial response, which has five value states, xe2x80x9c1xe2x80x9d and xe2x80x9c1+axe2x80x9d, and xe2x80x9cxe2x88x921xe2x80x9d and xe2x80x9cxe2x88x921xe2x88x92axe2x80x9d are not distinguished. Therefore an error occurs when a phase error is computed by the temporal judgment values. However, because the acquisition pattern is a 6T period repeat pattern, the error of phase computing is cancelled when phase error computing results for the three samples (symbols) are added. Therefore, the judgment states can be decreased, and phases can be acquired at high-speed even if the amplitude is not defined at acquisition.
The phase synchronization method in another embodiment of the present invention further comprises a step of retaining the temporal judgment value. The temporal judgment step is comprised of a step of selecting a first threshold value or a second threshold value according to the retention value, and a step of comparing the selected threshold value and the above mentioned sample output.
In this embodiment where the acquisition pattern is a 6T period repeat pattern, the judgment value after 3T can be estimated. Therefore the temporal judgment value is retained and the next judgment threshold level is selected. By changing the threshold level dynamically like this, judgment accuracy can be improved.
According to a phase synchronization method of another embodiment of the present invention, the temporal judgment step further comprises an initialization step of judging the sample output to be one of two values by the plurality of the sample output, and initializing the retention value. By doing this, a retention value can be automatically initialized.
A phase synchronization method of another embodiment of the present invention is a phase synchronization method for an extended partial response where phase synchronization is executed after extended partial response equalization is executed on a recording signal which was encoded by (1, 7) RLL codes and read from the recording medium. This phase synchronization method comprises a step of executing extended partial response equalization with a [1+(1+a)D+D2] (axe2x89xa70) characteristic on a recording signal, a step of sampling the equalization output by clocks, a step of classifying the above sample output into three groups of temporal judgment values [1+a, 1], 0, and [xe2x88x921,xe2x88x921xe2x88x92a], a judgment step of judging the above sample output to be [one of] five values from the high/low relationship with the sample outputs before and after the above sample output and the classified three groups of temporal judgment values, an error computing step of computing the phase error from the five-value judgment value and the above sample output, and a clock generation step of generating a clock with a phase according to the phase error.
In this embodiment, the number of judgment states is decreased at tracking. At tracking, where five values, 1+a, 1, 0, xe2x88x921 and xe2x88x921xe2x88x92a, exist, a judgment error tends to occur between [1+a and 1] and [xe2x88x921 and xe2x88x921xe2x88x92a], so the sample output is judged to be one of the three groups, [1+a, 1], 0 and [xe2x88x921,xe2x88x921xe2x88x92a].
Then to distinguish between [1+a and 1] and [xe2x88x921 and xe2x88x921xe2x88x92a], a state transition of (1, 7) RLL codes is used. In other words, (1, 7) RLL codes have regularity in the state of the sample and in the state of the samples before and after the sample. Using this, the high/low relationship between the sample value and the sample values before and after the sample value is judged to distinguish between [1+a and 1] and [xe2x88x921 and xe2x88x921xe2x88x92a]. Since the number of judgment states decreases, judgment accuracy improves. As a result, computing errors reflected in phase errors decrease, and phase synchronization can be executed stably.
It is preferable that in this judgment step, xe2x80x9c1+axe2x80x9d or xe2x80x9c1xe2x80x9d is judged from the high/low relationship between sample outputs before and after the sample output and the sample output when the above temporal judgment value is in the [1+a, 1] group, and xe2x80x9cxe2x88x921xe2x88x92axe2x80x9d or xe2x80x9cxe2x88x921xe2x80x9d is judged from the high/low relationship between sample outputs before and after the sample output and the sample output when the above temporal judgment value is in the [xe2x88x921, xe2x88x921xe2x88x92a] group.